2019 - Lorient > Posters

Posters présentés lors d’ARCHI 2019

Simulation of Software and Heterogeneous Hardware Systems: a Motor Speed Control System Case Study

• auteurs: Breytner Fernández-Mesa, Liliana Andrade, Frédéric Pétrot
• établissement: Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA
• lien(s): Résumé PDF

Secure Hardware Accelerators for Post Quantum Cryptography

• auteurs: Timo Zijlstra
• établissement: CNRS, Lab-STICC
• résumé: We implement post quantum public key encryption schemes on FPGA using High Level Synthesis. We focus on Module and Ring Learning with Errors (MLWE, RLWE) based cryptography, in which polynomial multiplication and multiplication of matrices of polynomials are the most costly operations. Parallelism is used to accelerate the computations.
• lien(s): Poster PDF

Fault-Tolerant Multiprocessor Scheduling Making Use of Backup Copy Technique

• auteurs: Petr Dobiáš, Emmanuel Casseau, Oliver Sinnen
• établissement: Univ. Rennes, Inria, CNRS, IRISA / Univ. of Auckland, PARC Lab, Department of Electrical and Computer Engineering
• résumé: Our research is aimed at studying fault-tolerant design of the real-time multi-processor systems and is in particular concerned with the dynamic mapping and scheduling of tasks on embedded systems. The effort is concentrated on scheduling strategy having reduced algorithm run-time and guaranteeing that, when a task is input into the system and accepted, then it is correctly executed prior to the task deadline. The chosen method makes use of the primary/backup approach and our objective is to enhance this approach using several refinements.
• lien(s): Poster PDF

Side channel attack against hardware shuffled AES implemenation

• auteurs: Ghita Harcha, Vianney Lapôtre, Cyrille Chavet, Philippe Coussy
• établissement: Université Bretagne Sud, Lab-STICC
• résumé: AES (Rajindael) is a symmetric cryptographic algorithm known to be mathematically secure, but have been proven to be vulnerable to side channel attacks. in this work we propose a lightweight hardware implementation, where the 16 independent operations and storage are shuffled to randomize the power consumption and complexify side channel attack.
• lien(s): Poster PDF

QoS driven dynamic partial reconfiguration: a tracking case study

• auteurs: Julien Mazuet, Dominique Heller, Catherine Dezan, Michel Narozny, Jean-Philippe Diguet
  
• établissement: Thales LAS-France, Lab-STICC, CNRS, Université de Bretagne Sud / Université de Bretagne Occidentale
  
• liens: Poster PDF